In an active matrix display, each of scan lines and each of data lines are intersected to each other to form an active matrix. Generally, by using a progressive scanning method, gates of respective gate lines are turned on sequentially, and voltages on data lines are written into pixels. A method of integrating line scanning driving circuits on the display backplane has narrow-frame and low-cost advantages and has been used in most of the Liquid Crystal Displays (LCDs) and Active Matrix Organic Light Emitting Diodes (AMOLEDs).
Currently, there are many technologies for manufacturing a display device backplane, such as a-Si (amorphous silicon) Thin Film Transistors (TFT), Low Temperature Poly-Silicon (LTPS) TFTs, Oxide TFTs and the like. The a-Si TFTs are more mature and low-cost but have low mobility and low stability. The LTPS TFTs have fast speed and good stability, but also have poor uniformity and high cost, and are not suitable for the preparation of large-size panels. Oxide TFTs have high mobility, good uniformity and low cost, and are the technology most suitable for a large-size panel display. However, current-voltage (I-V) transferring characteristics of oxide TFTs are usually of depletion type. That is, when a gate-source voltage (Vgs) of an oxide TFT is zero, it is still in an ON state. If Gate Driver on Array (GOA) of the oxide TFTs continues to adopt the a-Si GOA circuit, a result that the TFTs cannot be completely turned off, causing multiple outputs, will occur.
A depletion-type thin film transistor (TFT) causes great difficulty for integrating shift registers on a display device backplane. FIG. 1A is a diagram showing a structure of a conventional shift register. In FIG. 1A, all transistors are n-type thin film transistors. As shown in FIG. 1A, the conventional shift register includes a first output transistor T1, a second output transistor T2, a first control module 11 controlling T1 and a second control module 12 controlling T2. Except for the last level shift register, an output end of each level shift register is connected to an input end of a next shift register, and alternately controlled by two clock signal CLK1, CLK2 of which duty ratios are 50% Amplitudes of all input signals and control signals are VGL˜VGH. Here, the VGL is a low level while the VGH is a high level. The first output transistor T1 is connected to a clock signal CLKB and an output end OUT(n), and plays a role of transmitting the high level. The second output transistor T2 is connected to a low level output end which outputs the low level VGL and the output end OUT(n), and plays a role of transmitting the low level.
As shown in FIG. 1B, a work process of the shift register can be divided into three stages as follows.
The first stage is a pre-charge stage, in which when an output end OUT(n−1) of previous level shift register generates a high level pulse, the node PU (a node which is connected to a gate electrode of the transistor T1, i.e., the pulling up-node) is controlled to be charged to the high level VGH, while the node PD (a node which is connected to a gate electrode of the transistor T2, i.e., the pulling down-node) is controlled to be charged to the low level VGL; and at this time, the transistor T1 is turned on, so as to transmit the low level of CLKB to the output end OUT(n), while the transistor T2 is turned off.
The second stage is an evaluation stage. In a next clock cycle, the node PU is changed into a floating state, that is, all the transistors of the first output control module connected thereto are turned off so that no signal is transmitted thereto. The CLKB is changed from the low level to the high level. Along with the rise of the output voltage, the voltage of the node PU is bootstrapped to a higher level by a capacitor connected between the gate electrode of the transistor T1 and the output end OUT(n), thus ensuring that there is no threshold loss in the output voltage of the output end OUT(n). At this time, the node PD remains at the low level, so that the transistor T2 is turned off, preventing the high level outputted by the output end OUT(n) from leakage through T2.
The third stage is a reset stage, that is, in another next clock cycle; CLKB is changed into the low level while CLK is changed into the high level. So the node PU is discharged to the low level, the node PD is recharged to the high level. At this time, the transistor T1 is turned off and the transistor T2 is turned on, so that the output voltage of the output end OUT(n) maintains the low level by the transistor T2.
As shown in FIG. 1B, the node PU and the node PD forms a reciprocal relationship, so as to avoid transistor T1 and T2 being turned on simultaneously which will result in an abnormal output.
However, if the transistors T1 and T2 in FIG. 1A are depletion-type transistors, there will be a larger distortion generated in the output. Firstly, in the evaluation stage, the voltage of the node PU is high so that the transistor T1 is turned on. Although the voltage of the node PD is discharged to the low level VGL, yet due to depletion-type characteristics of the transistor T2, the transistor T2 cannot be turned off even its Vgs is zero, resulting in a leakage current. That is, the transistors T1 and T2 are conductive simultaneously, so the high level outputted by the output end OUT(n) depends on a resistance divided voltage of the transistors T1 and T2, which is typically much lower than a normally-required high level. Therefore, the normal operation of the next level shift register is affected, that is, the failure of the next level shift register may be caused. Secondly, in the reset stage, the voltage of the node PU is low while the voltage of the node PD is high, and the output voltage of the output end OUT(n) is low. But since the transistor T1 is a depletion-type transistor, the transistor T1 is always conductive (ON). If CLKB is changed to a high level, a high level pulse will generated in the output voltage of the output end OUT(n), the potential thereof depends on a resistance divided voltage of the transistors T1 and T2. A normal waveform of the output voltage of the output end OUT(n) is as shown in solid lines in FIG. 1C, a distorted waveform of the output voltage of the output end OUT(n) is as shown in broken lines in FIG. 1C.
In addition to the first output transistor T1 and the second output transistor T2, depletion-type TFTs in an internal control circuit will also cause an output failure. As shown in FIG. 2A, the second control module is a pulling-down control module, and the first control module contains transistors T3 and T4. The transistors T3 and T4 are depletion-type transistors, wherein the transistor T3 is connected to an output end OUT (n−1) of a previous level shift register and the node PU (the node connected to the gate electrode of T1). The transistor T3 plays a role of charging the node PU to a high level in the pre-charge stage. A gate electrode of the transistor T4 is connected to a reset signal Rst. The transistor T4 is connected to the node PU and a low level output end outputting the low level VGL. The transistor T4 plays a role of pulling down the voltage of the node PU in the reset stage. The depletion-type transistors T3 and T4 will be conductive (ON) in the evaluation stage, pulling down the voltage of the node PU, so that the transistor T1 is caused to be not fully turned on, and the high level outputted by the output end OUT(n) is affected, as shown in broken lines in FIG. 2B.
In summary, there is a need of improving the circuit structure to solve the effect of depletion-type TFTs on the output of the shift register.